RTL Design
Micro-architecture to clean RTL implementation, focused on quality and performance.
- Micro-architecture and RTL development
- Interface design and system modeling
- Low-power and high-performance design
Training & Education — Courses
A talent development initiative focused on creating industry-ready semiconductor engineers across RTL, DV, and PD.
Design Verification
UVM methodology, debug, coverage closure, and best practices.
- UVM methodology and testbench development
- Protocol verification (PCIe, DDR, CXL, NVLink)
- Coverage-driven verification and debug
Physical Design
RTL-to-GDS flow, timing closure, MMMC, and signoff discipline.
- RTL-to-GDSII flow
- PnR, CTS, STA, and signoff methodologies
- Backend flow automation
Outcome
Engineers trained through Training & Education are equipped to contribute to ASIC and SoC development programs, high-speed interface verification, backend implementation, and automation workflows.