Course: Physical Design (PD)

Learn RTL-to-GDS flow, timing closure fundamentals, MMMC, and signoff discipline for high-performance designs.

Who it’s for

Engineers who want a structured path into backend implementation and signoff-oriented thinking.

Prerequisites

Digital design basics + ability to read reports/logs. Scripting familiarity helps (Tcl/Python).

Outcome

A complete mini-flow walkthrough (floorplan → route → STA) with a signoff checklist and convergence notes.

Curriculum

Structured modules covering core physical design flow and timing closure practices.

RTL-to-GDS overview

  • Inputs: netlist, constraints, libs, tech files
  • What “closure” really means
  • Common bottlenecks and risk areas
  • Deliverables and hand-offs

Floorplanning

  • Die/core sizing, utilization, aspect ratio
  • Macro placement strategy
  • Power plan basics
  • Congestion awareness

Placement & CTS

  • Placement quality metrics
  • Clock tree strategy and constraints
  • Hold fixing mindset
  • ECO loops

Routing

  • Global vs detailed routing
  • DRC awareness, antenna basics
  • Shielding and critical nets
  • Congestion-driven refinements

Signoff essentials

  • STA: setup/hold, OCV, derates
  • SI/noise basics
  • IR/EM overview
  • PV: DRC/LVS concepts

Automation

  • Tcl flow scripting patterns
  • MMMC setup templates
  • Regression mindset for backend
  • Data-driven convergence notes
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