Physical Design Blog

RTL-to-GDS flow breakdown, timing closure strategies, PnR and signoff methodologies, and advanced node challenges.

Timing closure: a practical loop

A repeatable way to approach setup/hold closure and reduce churn.

  • Constraint sanity checks
  • Fix ordering: constraints → logic → placement → CTS
  • ECO hygiene
  • Regression and reproducibility

MMMC: structuring your corners

How to keep corners manageable and meaningful.

  • Corner selection principles
  • Derates and OCV basics
  • Report review checklist
  • Common pitfalls

Advanced nodes: what changes

Where the effort shifts at 7nm/FinFET and beyond.

  • Signal integrity awareness
  • IR/EM constraints
  • Congestion + routing
  • Signoff tool alignment