Course: Design Verification (DV)

Learn UVM methodology, debugging, coverage closure, and verification planning — aligned to industry SoC flows.

Who it’s for

Engineers who want to build verification fundamentals and become productive on UVM-based environments.

Prerequisites

Digital design basics + SystemVerilog fundamentals (or the RTL course).

Outcome

A reusable UVM testbench for a small IP, with coverage closure, assertions, and debug notes.

Curriculum

Structured modules focused on practical verification planning, implementation, and closure.

Verification planning

  • Requirements → test plan
  • Coverage goals and signoff definition
  • Testbench architecture overview
  • Debug workflow and triage

UVM fundamentals

  • Components, phases, objections
  • Sequences, drivers, monitors
  • Scoreboards and reference models
  • Configuration database patterns

Coverage & assertions

  • Functional vs code coverage
  • Coverage-driven verification
  • SVA basics (safety + liveness)
  • Common assertion patterns

Protocols (choose)

  • AXI/APB: handshake + ordering basics
  • DDR/PCIe/CXL: verification mindset
  • BFMs, monitors, checkers
  • Reusable components

Advanced DV (overview)

  • Power-aware verification (UPF/CPF)
  • Formal verification (FPV/SEC)
  • Gate-level simulation basics
  • SoC-level bring-up strategies

Project lab

  • Build a UVM env for a small IP
  • Regression + coverage closure
  • Debug diary and root-cause writeups
  • Demo + signoff checklist
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