Who it’s for
Students and early-career engineers who want hands-on RTL design skills with industry workflows.
Course: RTL Design
Micro-architecture → clean RTL. Build the fundamentals you need to contribute on real silicon programs.
Prerequisites
Basic digital design (FSMs, pipelining) and comfort with Linux + scripting basics.
Outcome
A portfolio-ready RTL project with testbench, lint/CDC checklist, and a clear micro-architecture spec.
Curriculum
Structured modules to build RTL design fundamentals and practical implementation skills.
RTL foundations
- Verilog/SystemVerilog essentials
- Combinational vs sequential modeling
- Reset strategy, clocking, and timing basics
- Good coding style and readability
Micro-architecture
- Spec → blocks → interfaces
- Pipelining & throughput/latency trade-offs
- Arbitration, queues, and backpressure
- Performance modeling (lightweight)
Low power & quality
- Clock gating basics, enables, and safe gating rules
- Assertions for design intent (SVA intro)
- Lint, CDC/RDC awareness, review checklists
- Documentation: spec + diagrams
Interfaces (choose)
- AMBA basics: AXI/APB handshakes (intro)
- FIFO design patterns
- Credit-based flow control (overview)
- SoC integration considerations
Project build
- Pick a block: DMA / arbiter / cache-like pipeline
- Write spec + micro-architecture
- Implement RTL + unit tests
- Demo + design review
Industry workflow
- Git, code reviews, and branching discipline
- Makefile basics and reproducible builds
- Regression mindset
- Hand-off artifacts