Physical Design Engineer
RTL-to-GDS implementation with signoff discipline.
- Floorplanning, placement, CTS, routing
- MMMC, STA, SI, IR/EM awareness
- ECO methodology and convergence
- Automation / flow scripting (Tcl preferred)
Careers
Join an engineering-first team focused on end-to-end silicon delivery: RTL, DV, PD, FPGA, and automation.
Design Verification Engineer
UVM-based verification, debug, and coverage closure.
- UVM testbench development (agents, scoreboards)
- SVA assertions; coverage-driven verification
- Debug, triage, and root-cause analysis
- Protocol familiarity: AXI/APB, PCIe/DDR/CXL (plus)
FPGA Engineer
Prototyping, bring-up, and ASIC-to-FPGA correlation.
- Vivado synthesis/implementation and constraints
- Debug (ILA/probes), timing closure
- Board-level validation and interface bring-up
- Automation scripting and regression mindset
How to apply
Use the “Apply via email” button for the role, or email your resume to [email protected] with the role name in the subject.