- Floorplanning, placement, CTS, routing
- Timing closure & signoff (STA, SI, IR/EM)
- Multi-voltage / low-power implementation
- ECO and convergence methodologies
Physical Design (PD)
Complete RTL-to-GDSII implementation with strong expertise in advanced nodes and high-performance designs.
- Nodes: 7nm / 10nm / FinFET (and beyond)
- CoWoS and advanced packaging awareness
- MMMC setup and signoff integration
- Data-driven convergence approaches
- Automated PnR flows (ICC2 / Innovus)
- Backend regression and validation frameworks
- Report analytics and dashboards
- Repeatable signoff checklists